gitlab.telecom-paris.fr / renaud.pacalet / sab4z
A simple example design for Zynq-based boards. VHDL design of custom HW mapped in Programmable Logic, Linux - Busybox - Buildroot SW stack, user SW applications interacting with custom hardware, Linux drivers, SW and HW debugging.
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License: cecill-2.1
Language:
Dependencies parsed at: Pending
Created at: about 8 years ago
Updated at: 12 months ago
Pushed at: 12 months ago
Last synced at: about 1 year ago
Topics: Buildroot, Linux, U-Boot, VHDL, Xilinx Zynq
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