sen/dev-projects/cfglut5-sbox

16 nibbles (64 bits) parallel sboxes using Xilinx CFGLUT5 primitive

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sen/dev-projects/asciidoc-to-markdown

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sen/dev-projects/tei0001-03-16-c8a

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sen/dev-projects/sv_sim_uart

SystemVerilog simulation environment for an UART

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sen/dev-projects/rtl-ator

Example of Verilog/SystemVerilog + SystemC TB simulation using Verilator

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